This invention relates to an integrated injection logic semiconductor device.
The integrated injection logic (I.sup.2 L) semiconductor device has become noted in recent years because it has such advantages that its construction is simpler, can be manufactured at higher yield, can be integrated more densely and has smaller power delay product when compared with a conventional transistor-transistor logic device. Usually, the I.sup.2 L device is constructed such that a switching transistor and an injector for injecting minority carriers into the base region of the switching transistor are formed on the same semiconductor substrate and the input to the I.sup.2 L device is controlled while the minority carriers are injected into the base region of the switching transistor, thereby to efficiently control the collector output of the vertical transistor which is the output of the I.sup.2 L device.
In a conventional I.sup.2 L semiconductor device, an N type layer of a low impurity concentration is formed by an epitaxial growth process on an N.sup.+ type semiconductor substrate of a high impurity concentration and then first and second P type regions are formed in the N.sup.- type layer by diffusion. The first P type region serves as an injector region for injecting holes. An N.sup.+ region is formed in the second P type region. With this construction a PNP lateral transistor is obtained wherein the emitter, base and collector regions thereof are constituted by the first P type region, the N.sup.- type layer and the second P type region, respectively, while at the same time a vertical NPN transistor is obtained wherein the emitter, base and collector regions are constituted by the N.sup.- type layer, the second P type region and the N.sup.+ type region, respectively.
In this manner, since the I.sup.2 L semiconductor device is constructed such that the collector region of the lateral transistor and the base region of the vertical transistor are common and that the vertical transistor operates as if the emitter and collector regions of a conventional planar transistor were interchanged, the I.sup.2 L semiconductor device can not operate efficiently unless making large as far as possible the current amplification coefficient of the lateral transistor and making large the current amplification coefficient in the reverse direction of the vertical transistor. However, since the N.sup.- type layer is used in common for the base region of the lateral transistor and the emitter region of the vertical transistor it is impossible to simultaneously increase the current amplification coefficients of both transistors. Moreover, since the width of the base region of the lateral transistor is increased in the direction of depth it is impossible to sufficiently increase the transfer efficiency of holes in the base region. Further, since the emitter region of the vertical transistor comprises a low impurity density N.sup.- type layer, and the base region has higher impurity concentration than the emitter region, it is impossible to sufficiently improve the efficiency of carrier injection from the emitter region. As a consequence, with the prior art I.sup.2 L semiconductor device described above it is impossible to improve its current amplification coefficient beyond a definite limit with the result that the power delay product increases.